The present invention relates to a 2-bit error correcting circuit arrangement using cube circuits, more particularly, a BCH code check matrix H in which (n+1) cube circuits as check circuits, each corresponding to each of the data bits d.sub.o to d.sub.n, are so arranged in parallel that the error correction may be carried out quickly, and the same circuit arrangement may be adopted for said check circuits.
In order to improve the reliability of a data processing system, error correcting codes are widely used. Among others, a BCH code with a 2-bit error correcting function has been adopted in error correcting systems. Various systems, such as the one proposed by R. T. Chien, are well known for decoding said BCH code. Such systems will be generally referred to hereinbelow as conventional systems.
However, said conventional systems use in general shift registers and cannot correct errors before such registers have been shifted by plural clocks (which will be described later with reference to FIG. 1). Accordingly, when attempts have been made to develop the conventional system, for example, the one by R. T. Chien, so that high speed processing may be done in parallel for error corrections, the system will necessarily become a complicated one as can be seen with reference to FIG. 2. In this case, the individual circuits x.alpha..sup.44, x.alpha..sup.43 . . . x.alpha..sup.3 illustrated in FIG. 2 will take different forms, resulting in a high cost and a complicated structure of the circuit arrangement. This becomes a further obstacle for large-scale integration of such a circuit.